Many types of opto-electronic modules comprise a number of separate optical and electrical components that require precise placement relative to one another. A silicon (or glass) carrier substrate (sometimes referred to as an interposer) is generally used as a support structure to fix the location of the components and may, at times, also provide the desired electrical or optical signal paths between selected components. In other arrangements, the optical and electrical components may be directly placed on and within a silicon surface layer of a silicon-on-insulator (SOI)-based optical platform. Regardless of the structure of the support arrangement, optical alignment between various optical components is required to ensure that the integrity of the optical signal path is maintained.
Active alignment processes generally require the use of visual systems in combination with micro-positioning arrangements to adjust the position of a first optical component with respect to another optical component. These active alignment arrangements are generally slow and expensive, impacting throughput and cycle time in assembly operations. In contrast to active alignment, “passive” optical alignment arrangements may be utilized, which rely on matching and mating alignment fiducials formed on both the substrate and each optical component. As one drawback, passive alignment arrangements add cost and complexity to the fabrication of the individual components by requiring the additional steps associated with forming the fiducials on each optical component. Moreover, these opto-electronic assemblies are typically built as individual units and, as a result, the need to perform optical alignment (active or passive) on a unit-by-unit basis becomes expensive and time-consuming.
Indeed, as the demand for opto-electronic modules continues to increase, the individual unit assembly approach has become problematic. Wafer level packaging is considered to be a more efficient and cost-effective approach, with one exemplary arrangement of wafer level packaging disclosed in our co-pending application Ser. No. 13/463,408, filed May 3, 2012 and herein incorporated by reference.
In our co-pending application, a silicon wafer is utilized as a “platform” (i.e. interposer or carrier) upon which all of the components for a multiple number of opto-electronic modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path for optical alignment purposes. The use of a single silicon wafer as a platform for a large number of separate modules allows for a wafer level assembly process to efficiently assemble a large number of modules in a relatively short period of time.
While the use of wafer level assembly does improve the efficiency of the fabrication process, the use of an active alignment process remains a drawback in terms of its complexity and low throughput. As the size and complexity of opto-electronic assemblies continues to increase, the ability to find locations on both the substrate and the optical components to create alignment fiducials for passive alignment alternatives becomes increasingly difficult.